Voltage-divider bias

Model equations and assumptions

1. Course approximation: V_B = V_CCR₂/(R₁ + R₂), with base loading neglected.
2. Emitter relation: V_E = V_B − 0.70 V and I_C ≈ I_E = V_E/R_E.
3. Collector-emitter Kirchhoff’s voltage law (KVL): V_CC − I_CR_C − V_CE − I_ER_E = 0.
4. Design constraint: R_C + R_E = (V_CC − V_CEQ)/I_CQ. The required Q point specifies VCEQ and ICQ.

VB, VE and VC are the base, emitter and collector voltages relative to GND. VBE = VB − VE; VCE = VC − VE. IB, IC and IE are the base, collector and emitter currents.

The Q point is the calculated DC condition before an applied signal. Course approximation uses a constant base-emitter drop and neglects physical base current during resistor selection. Finite-beta mode includes divider loading and applies Kirchhoff’s current law (KCL): IE = IC + IB. The active current gain β = IC/IB.